Isolation structure for strained channel transistors

ABSTRACT

A method and system is disclosed for forming an improved isolation structure for strained channel transistors. In one example, an isolation structure is formed comprising a trench filled with a nitrogen-containing liner and a gap filler. The nitrogen-containing liner enables the isolation structure to reduce compressive strain contribution to the channel region.

TECHNICAL FIELD

The present disclosure relates generally to the field of semiconductordevices, and more particularly to strained channel transistors withenhanced performance using improved isolation regions and the method formaking same.

BACKGROUND

Size reduction of the metal-oxide-semiconductor field-effect transistor(MOSFET), including reduction of the gate length and gate oxidethickness, has enabled the continued improvement in speed performance,density, and cost per unit function of integrated circuits over the pastfew decades. To enhance transistor performance further, strain may beintroduced in the transistor channel for improving carrier mobility.Therefore, strain-induced mobility enhancement is another way to improvetransistor performance in addition to device scaling. Several existingapproaches of introducing strain in the transistor channel region havebeen proposed.

There are several existing approaches of introducing strain in thetransistor channel region to enhance further transistor performance. Inone conventional approach, a relaxed silicon germanium (SiGe) bufferlayer 102 is provided beneath the channel region, as shown in FIG. 1(a).The relaxed SiGe buffer layer 102 has a larger lattice constant comparedto relaxed Si 104, and a thin layer of epitaxial Si 106 grown on relaxedSiGe 102 will have its lattice stretched in the lateral direction, i.e.it will be under biaxial tensile strain. This is illustrated in FIG.1(b). Therefore, a transistor formed on the epitaxial strained siliconlayer 106 will have a channel region that is under biaxial tensilestrain. In this approach, the relaxed SiGe buffer layer 102 can bethought of as a stressor that introduces strain in the channel region.The stressor, in this case, is placed below the transistor channelregion. Significant mobility enhancement has been reported for bothelectrons and holes in bulk transistors using a silicon channel underbiaxial tensile strain. In the abovementioned approach, the epitaxialsilicon layer 106 is strained before the formation of the transistor.Therefore, there are concerns about possible strain relaxation uponsubsequent CMOS processing where high temperatures are used. An exampleof a high temperature process step in CMOS processing is the formationof an isolation structure, such as shallow trench isolation, toelectrically isolate devices from one another.

In a conventional shallow trench isolation process 200, as shown in FIG.2, a silicon oxide liner 202 is typically thermally grown attemperatures ranging from 900 to 1100 degrees Celsius. The hightemperatures can potentially cause strain relaxation and reduce thetensile strain in the tensile strained silicon channel region 204. Byusing the conventional oxide-filled trench isolation structure 206 withthe strained silicon substrate 208, as shown in FIG. 2, the trenchisolation structure 206 contributes a significant compressive straincomponent 210 to the channel region 204. The compressive straincomponent 210 contributed by the oxide-filled trench isolation structure206 cancels out a portion of the tensile strain component of the tensilestrained silicon substrate 208 constituting the channel region 204. Withthe reduction of the tensile strain in the channel region 204 of thetransistor, the strain-induced performance enhancement is reducedsignificantly. The compressive strain results from sidewall oxidationand volume expansion of the silicon oxide material in the trench.

What is needed is an improved isolation structure for strained channeltransistors and the method for making same.

SUMMARY OF INVENTION

In view of the foregoing, the present disclosure provides a system andmethod for forming an improved isolation structure for strained channeltransistors.

In one example, an isolation structure is formed comprising a trenchfilled with a silicon oxide liner, a nitrogen-containing liner, and agap filler. In another example, an isolation structure is formedcomprising a trench filled with a nitrogen-containing liner and a gapfiller. The nitrogen-containing liner enables the isolation structure toreduce compressive strain contribution to the channel region. Thenitrogen-containing liner minimizes confined volume expansion andreduces compressive stress in the surrounding active region.

The present disclosure provide isolation structures with reducedcompressive strain contribution and reduced thermal budget in a tensilestrained silicon substrate. Another object of the present disclosure isto teach a method of engineering the strain in the channel of thetensile strained transistor by engineering the isolation structure toimprove transistor performance.

These and other aspects and advantages will become apparent from thefollowing detailed description, taken in conjunction with theaccompanying drawings, illustrating by way of example the principles ofthe disclosure.

BRIEF DESCRIPTION OF DRAWINGS

The present disclosure will be more clearly understood after referenceto the following detailed description of preferred embodiments read inconjunction with the drawings, wherein:

FIGS. 1(a)-(b) illustrate the cross-section of a conventional strainedsilicon transistor with a relaxed SiGe and the illustration of theorigin of strain in the Si/SiGe hetero-structure, respectively.

FIG. 2 illustrates a transistor formed in an active region isolatedshallow trench isolation (STI).

FIGS. 3(a)-(b) illustrate a novel low-stress isolation structure for thestrained silicon transistor according to one example of the presentdisclosure.

FIGS. 4(a)-(e) illustrate a first method of manufacturing a novellow-stress isolation structure for the strained silicon transistoraccording to another example of the present disclosure.

FIGS. 5(a)-(e) illustrate a second method of manufacturing a novellow-stress isolation structure for the strained silicon transistoraccording to another example of the present disclosure.

FIGS. 6(a)-(e) illustrate a third method of manufacturing a novellow-stress isolation structure for the strained silicon transistoraccording to another example of the present disclosure.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

As illustrated below, the structure of and methods are disclosed belowfor the manufacture of an improved isolation structure with reducedcompression strain contribution to the channel region and/or reducedthermal budget. Several embodiments are shown as illustrated examples.

First Embodiment

FIG. 3(a) illustrates a first structure embodiment of the presentdisclosure. The isolation structure 300 illustrated in FIG. 3(a)comprises a trench 302 filled with a silicon oxide liner 304, anitrogen-containing liner 306, and a gap filler 308. The depth of thetrench 302 is in the range of 2000 to 6000 angstroms. Thenitrogen-containing liner 306 contributes to the reduction ofcompressive strain contribution to the channel region 310. Thenitrogen-containing liner 306 acts as an oxidation mask, preventingfurther oxidation of the trench sidewalls 312 in subsequent processingsteps where, because of its slow diffusion rate in thenitrogen-containing liner 306, oxygen is present in the processingambient. The nitrogen-containing liner 306 minimizes confined volumeexpansion and reduces compressive stress in the surrounding activeregion. Prior art tensile strained silicon transistors do not employ thenitrogen-containing liner 306 and as a result have reduced tensilestrain and compromised transistor performance. According to onepreferred embodiment of this disclosure, the nitrogen-containing liner306 is comprised of silicon nitride, Si₃N₄. The nitrogen-containingliner 306 may also be comprised of a silicon oxynitride SiO_(x)N_(y)material or a nitrogen-doped silicon oxide material, where the atomicpercentage of nitrogen in the nitrogen-containing liner 306 may be inthe range of 5 to 60 percent (%). It is understood, however, that othermaterials with oxygen diffusion rates lower than that of silicon oxidemay be used. By employing an isolation structure 300 with anitrogen-containing liner 306, the compressive strain contribution bythe isolation structure 300 to the channel region 310 is reduced, sothat the channel region 310 is entirely or almost entirely strained bythe relaxed silicon-germanium (SiGe) layer 314 underlying the channelregion 310. The present embodiment provides a strained silicon layer 316totally tensile strained by the underlying relaxed SiGe layer 314 andcan be negligibly compressive-strained by the isolation structure 300.

Second Embodiment

FIG. 3(b) illustrates a second structure embodiment of the presentdisclosure. The second structure embodiment of FIG. 3(b) differs fromthe first structure embodiment described above and illustrated in FIG.3(a) in that the nitrogen-containing liner 306 in FIG. 3(b) is in directcontact with the trench sidewall surface 312. In other words, thesilicon oxide liner 304 of the first embodiment in FIG. 3(a) is not usedin this embodiment. By eliminating the silicon oxide liner 304, thisstructure further reduces the thermal budget associated with theisolation structure 300 formation process and further improves theability of the nitrogen-containing liner 306 to block oxidation of thetrench sidewall surface 312. In addition, it is also possible that thenitrogen-containing liner 306 may exert a beneficial strain on thechannel region 310. For example, the nitrogen-containing liner 306itself may be formed under tensile stress, and therefore induces avertical compressive strain on the region of the strained silicon layer316 in its immediate vicinity. This vertical compressive strain providesan additional biaxial tensile strain component to the channel region310. Therefore, the preferred embodiment of FIG. 3(b) reduces thecompressive strain contribution by the isolation structure 300 on thechannel region 310 and potentially could strengthen the in-plane tensilestrain component 318 that is beneficial to the strained channeltransistor 320 for additional boost in speed performance.

Third Embodiment

FIGS. 4(a)-(e) illustrate a first method embodiment of the presentdisclosure, describing a process flow for forming strained silicontransistors with reduced thermal budget and reduced compressive straincontribution by the isolation structure to the channel region. Theisolation structure 400 preferably comprises a nitrogen-containing liner402 in direct contact with the trench sidewall surface 404. Thenitrogen-containing liner 402 can be a single silicon nitride layer or asilicon oxynitride layer 406. The nitrogen content of thenitrogen-containing liner 402 may be in the range of 5 to 60 percent (%)by atomic percentage. A substrate comprising a strained silicon layer408 overlying a relaxed silicon-germanium (SiGe) layer 410 is used asthe starting material. Such a substrate may further comprise a gradeSiGe buffer layer 412, and may further comprise a silicon substrate 414underlying the grade SiGe buffer layer 412. A first patterned mask isformed on the substrate, and the trenches 416 are etched into thesubstrate, as shown in FIG. 4(a). The first patterned mask is preferablycomprised of a silicon nitride layer 406 overlying a pad oxide layer418. The pad oxide layer 418 is preferably comprised of silicon oxide. Aconventional anisotropic plasma etching with fluorine chemistry is usedto etch the isolation trenches 416.

FIG. 4(b) illustrates the formation of a nitrogen-containing liner 402.The nitrogen-containing liner 402 may be formed by low-pressure chemicalvapor deposition (LPCVD), for example. The nitrogen-containing liner 402is preferably formed to a thickness of about 10 to 500 angstroms,although smaller or larger thicknesses than the specified range may beused. The nitrogen-containing liner 402 is preferably a high tensilestress conformal nitride, Si₃N₄, liner. The chemical vapor depositionprocess may use precursor gases such as ammonia and silane. The typicaldeposition temperature is between 550 and 900 degrees Celsius. A trenchfiling material, the gap filler 420, preferably silicon oxide, is filledinto the trenches 416. The gap filler 420 may be a combination of trenchfilling materials, such as a combination of CVD silicon oxide and CVDpoly-crystalline silicon. After deposition, the gap filler 420 isdensified by either a pyrogenic oxidation anneal at a temperature of 800degrees Celsius or a conventional annealing step in argon ambient at1000 degree Celsius.

The cross-section in FIG. 4(c) illustrates the chemical mechanicalpolishing step performed to planarize the surface of the wafer. Thefirst patterned mask can be removed. In the preferred embodiment, thefirst patterned mask comprises a silicon nitride or pad nitride on asilicon oxide stack or pad oxide. The cross-section in FIG. 4(d)illustrates the removal of the first patterned mask by an etch in hotphosphoric acid followed by an etch in dilute hydrofluoric acid. It thusexposes the nitrogen-containing liner 402 through two recesses 403. Thestrained Si areas 408 on both sides of the trench are now covered by thepad oxide 418. Although not shown, if there are materials between therelaxed Si and the pad oxide layer, they can also be removed.

The cross-section in FIG. 4(e) illustrates the stripping of the padoxide 418 by aqueous HF. Transistors may then be formed in the activeregions with a surface comprising the strained silicon layer 408.

Fourth Embodiment

FIGS. 5(a)-(e) illustrate a second method embodiment of the presentdisclosure, describing a process flow for forming strained silicontransistors with reduced thermal budget and compressive straincontribution by the isolation structure to the channel region. Theisolation structure 500 preferably comprises a nitrogen-containing liner502 overlying a silicon oxide liner 504. In this method embodiment, thesilicon oxide liner 504 is formed by chemical vapor deposition,preferably plasma-enhanced chemical vapor deposition (PECVD). Thesilicon oxide liner 504 is in direct contact with the trench sidewallsurface 506. A substrate comprising a strained silicon layer 508overlying a relaxed silicon-germanium (SiGe) layer 510 is used as thestarting material. The starting substrate may further comprise a siliconsubstrate 512 underlying a graded SiGe buffer layer 514. A firstpatterned mask is formed on the substrate, and trenches 516 are etchedinto the substrate, as illustrated in FIG. 5(a). The first patternedmask is preferably comprised of a silicon nitride layer 518 overlying apad oxide layer 520. The pad oxide layer 520 is preferably comprised ofsilicon oxide. A conventional anisotropic plasma etching with fluorinechemistry is used to etch the isolation trenches 516. Following theformation of the trenches 516, the wafer may be subject to a chemicaltreatment to result in a pull back of the first patterned mask. The pullback distance 522, as illustrated in FIG. 5(a), may be in the range of50 to 1000 angstroms. The chemical treatment may be a wet etch processin hot phosphoric acid at a temperature in the range of 150 to 180degrees Celsius. The chemical treatment may further comprise a wet etchin dilute hydrochloric acid. A corner rounding process may be performedproducing rounded corners 524. The rounded corners 524 may be convexrounded corners (top corners at the trench 516 edge) or concave roundedcorners (bottom corners at the trench 516 bottom). The corner roundingprocess is preferably an annealing process at temperatures in the rangeof 700 to 950 degrees Celsius in a gaseous ambient. The gaseous ambientmay be comprised of hydrogen, helium, neon, argon, xenon, or anycombination thereof.

The cross-section illustrated in FIG. 5(b) involves the deposition ofthe silicon oxide liner 504, the deposition of the nitrogen-containingliner 502, and the deposition of the gap filler material 526. The gapfiller material 526 is preferably silicon oxide.

A planarization step, preferably using a chemical mechanical polishingprocess, is performed. The resulting cross-section is illustrated inFIG. 5(c). The pad nitride 518 is then removed. The resultingcross-section is illustrated in FIG. 5(d). The pad oxide 520 is thenremoved. The resulting cross-section is illustrated in FIG. 5(e).Transistors may then be formed in the active regions with a surfacecomprising the strained silicon layer 506.

Fifth Embodiment

FIGS. 6(a)-(e) illustrate a third method embodiment of the presentdisclosure, describing a process flow for forming strained silicontransistors with reduced thermal budget and compressive straincontribution by the isolation structure to the channel region. Theisolation structure 600 comprises a nitrogen-containing liner 602overlying a silicon oxide liner 604. The third method embodiment differsfrom the second method embodiment of the present disclosure in that thesilicon oxide liner 604 of the third method embodiment is formed by athermal oxidation process. The thermally grown silicon oxide liner 604is in direct contact with the trench sidewall surface 606. Since thegrowth of the thermal oxide results in rounded corners, the cornerrounding process is optional. A substrate comprising a strained siliconlayer 608 overlying a relaxed silicon-germanium (SiGe) layer 610 is usedas the starting material. A first patterned mask is formed on thesubstrate, and trenches 612 are etched into the substrate, asillustrated in FIG. 6(a). The first patterned mask is preferablycomprised of a silicon nitride layer 614 overlying a pad oxide layer616. The pad oxide layer 616 is preferably comprised of silicon oxide. Aconventional anistropic plasma etching with fluorine chemistry is usedto etch the isolation trenches 612. Following the formation of thetrenches 612, the wafer may be subject to a chemical treatment resultingin a pull back of the first patterned mask. The pull back distance 618,as indicated in FIG. 6(a), may be in the range of 50 to 1000 angstroms.The chemical treatment may be a wet etch process in hot phosphoric acidat a temperature in the range of 150 to 180 degrees Celsius. Thechemical treatment may further comprise a wet etch in dilutehydrochloric acid. A corner rounding process as previously described mayoptionally be performed.

The cross-section illustrated in FIG. 6(b) involves the thermal growthof a silicon oxide liner 604, the deposition of the nitrogen-containingliner 602, and the deposition of the gap filler material 620. The gapfiller material 620 is preferably silicon oxide.

A planarization step, preferably using a chemical mechanical polishingprocess, is performed. The resulting cross-section is illustrated inFIG. 6(c). The pad nitride 614 is then removed. The resultingcross-section is illustrated in FIG. 6(d). The pad oxide 616 is thenremoved. The resulting cross-section is illustrated in FIG. 6(e).Transistors may then be formed in the active regions with a surfacecomprising the strained silicon layer 608.

The above disclosure provides many different embodiments, or examples,for implementing different features of the present disclosure. Specificexamples of components, and processes are described to help clarify thepresent disclosure. These are, of course, merely examples and are notintended to limit the present disclosure from that described in theclaims. For example, while a shallow trench isolation is illustrated, itis understood that the present disclosure may be extended to otherisolation structures, which are improvements of the shallow trenchisolation structure. Accordingly, the specification and figures are tobe regarded in an illustrative rather than a restrictive sense.

While the present disclosure has been particularly shown and describedwith reference to the preferred embodiment thereof, it will beunderstood by those skilled in the art that various changes in form anddetail may be made therein without departing from the spirit and scopeof the present disclosure, as set forth in the following claims.

1. A strained channel transistor with at least one isolation structure,the transistor being formed on a semiconductor substrate comprising astrained silicon layer overlying a tensile strain forming buffer layer,the isolation structure comprising: an active region formed in thesemiconductor substrate; and at least one nitrogen-containing linerisolation region next to the active region.
 2. The transistor accordingto claim 1, wherein the isolation region is a shallow trench isolationregion with a trench depth in the range of 2000 to 6000 angstroms. 3.The transistor according to claim 1, wherein the nitrogen-containingliner has a thickness in the range of 10 to 500 angstroms.
 4. Thetransistor according to claim 1, wherein a channel region is formed inthe strained silicon layer of the active region with a source or drainregion formed between the channel region and the isolation region. 5.The transistor according to claim 1, wherein the tensile strain formingbuffer layer is a relaxed silicon-germanium layer.
 6. The transistoraccording to claim 5, wherein the substrate further comprises a gradedsilicon-germanium buffer layer underlying the relaxed silicon-germaniumlayer, the graded silicon-germanium buffer layer overlying a siliconsubstrate.
 7. The transistor according to claim 1, wherein the isolationregion further comprises an oxide liner underlying thenitrogen-containing liner.
 8. The transistor according to claim 1,wherein the isolation region includes a gap filler material.
 9. Thetransistor according to claim 1, wherein the nitrogen-containing linercomprises at least one of silicon nitride, silicon oxynitride, ornitrogen-doped silicon oxide.
 10. The transistor according to claim 1,wherein the nitrogen-containing liner has a nitrogen content of 5 to 60percent (%).
 11. The transistor according to claim 1, wherein a in-planetensile strain of a channel region of the active region is between 0.1%to 2%.
 12. A method of forming an isolation structure for strainedchannel transistors comprising: providing a semiconductor substratecomprising a strained silicon layer overlying a strain forming bufferlayer; forming a trench in the semiconductor substrate; forming anitrogen-containing liner in the trench; and filling the trench with agap filler material, wherein the nitrogen-containing liner reduces acompressive strain asserted on the strained silicon layer by the gapfiller material contained therein.
 13. The method according to claim 12,wherein the nitrogen-containing liner is comprised of silicon nitride orsilicon oxynitride.
 14. The method according to claim 12, wherein thenitrogen-containing liner has a nitrogen content of 5 to 60 percent (%).15. The method according to claim 12, wherein the nitrogen-containingliner has a thickness in the range of 10 to 500 angstroms.
 16. Themethod according to claim 12, further comprising the step of, after thestep of forming the trench, of forming a silicon oxide liner underlyingthe nitrogen-containing liner.
 17. The method according to claim 16,wherein the step of forming the silicon oxide liner is a thermaloxidation step or a chemical vapor deposition step.
 18. The methodaccording to claim 12, further comprising the step, after the step offorming the trench, of performing a corner rounding process step. 19.The method according to claim 18, wherein the corner rounding processstep is an anneal at a temperature in the range of 700 to 950 degreesCelsius in a gaseous ambient, the gaseous ambient.
 20. The methodaccording to claim 18, further comprising a step, after the step ofcorner rounding, of forming a silicon oxide liner.
 21. The methodaccording to claim 18, wherein the step of forming the silicon oxideliner is a thermal oxidation step or a chemical vapor deposition step.22. The method according to claim 18, wherein forming the trench in thesemiconductor substrate further includes forming a pull back of theopening of the trench.
 23. The method according to claim 22, wherein thepull back is in the range of 50 to 1000 angstroms.
 24. The methodaccording to claim 22, wherein the pull back is formed by a chemicaltreatment with a wet etch process in hot acid at a temperature in therange of 150 to 180 degrees Celsius.
 25. The method according to claim24, wherein the chemical treatment further includes a wet etch processin dilute hydrochloric acid.